1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of reducing material loss in isolation structures, such as trench isolation structures, during the process flow performed to grow channel semiconductor materials.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. One technique used to form STI structures initially involves growing a pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layer are patterned. Then, an etching process is performed to form trenches in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process, such as the well-known High Aspect Ratio Process (HARP) offered by Applied Materials, is performed to overfill the trenches with an insulating material such as silicon dioxide. The deposited silicon dioxide material is then typically densified by subjecting it to an anneal process in a furnace, e.g., about 1000° C. for a duration of about 30 minutes. The purpose of the densification process is to increase the etch resistance of the silicon dioxide material to later wet etching processes. Thereafter, a chemical mechanical polishing (CMP) process is performed using the pad nitride layer as a polish stop layer to remove the excess insulation material positioned outside of the trenches. Then, a subsequent deglazing (etching) process may be performed to insure that the silicon dioxide insulating material is removed from the surface of the pad nitride layer. This deglaze process may remove some of the material of the STI structures. Thereafter, a wet nitride strip process, e.g., a hot phosphoric acid process, is performed to selectively remove the pad nitride layer relative to the pad oxide layer and the STI structure. If desired, the pad oxide layer may also be removed at this time by performing a quick wet etching process using a dilute HF chemistry. Alternatively, the pad oxide layer may be left in place or removed at a later point in the process flow.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. One problem that arises with current processing techniques is that, after the STI regions are formed, at least portions of the STI regions are exposed to many subsequent etching or cleaning processes that tend to consume, at least to some degree, portions of the STI structures subjected to such etching processes. The attacks are not uniform across the surface of the STI structure due to, for example, masking only certain portions of the STI structure during some etching processes. As a result, there is an uneven loss of material in the STI structure, sometimes referred to as “divots.”
One illustrative situation where divots may be created in STI structures involves the formation of NFET and PFET transistor devices on the same substrate, i.e., CMOS (complementary metal oxide semiconductor) technology, due to different materials and construction techniques used in forming the two different types of devices. Typically, manufacturing integrated circuit devices using CMOS technology involves many masking operations wherein one of the device regions is masked, e.g., the N-active region, while the other region, e.g., the P-active region, is subjected to various processing operations, e.g., etching, selective deposition of materials, etc. Since the various mask layers used in manufacturing CMOS-based products typically only cover about half of the STI structures, the STI structures are subjected to different processing operations. As a result, undesirable divots are formed in STI structures in CMOS-based products.
FIGS. 1A-1H depict one illustrative prior art process flow wherein undesirable material loss may occur in isolation regions that are formed in the substrate. As shown in FIG. 1A, various isolation structures 12 have been formed in a semiconducting substrate 10 which thereby define an N-active region 10N and a P-active region 10P wherein an NFET device and a PFET device, respectively, will be formed. The substrate 10 may have a variety of configurations, such as the depicted bulk silicon configuration.
As depicted in FIG. 1A, a hard mask layer comprised of silicon dioxide 14 has been deposited on the surface 10S of the substrate 10. The hard mask layer 14 may be formed using traditional techniques, e.g., by performing a chemical vapor deposition (CVD) process, and its thickness may vary, e.g., it may have a thickness in the range of about 6 nm.
As shown in FIG. 1B, a first patterned mask layer 16, e.g., a patterned photoresist mask, is formed above the hard mask layer 14. The first patterned mask layer 16 covers the N-active region 10N and exposes the portion of the hard mask layer 14 that is positioned above the P-active region 10P for further processing. The first patterned mask layer 16 may be formed using traditional photolithography tools and techniques.
As shown in FIG. 1C, an etching process, such as a wet etching process using a dilute HF chemistry, is performed through the first patterned mask layer 16 to remove the exposed portions of the hard mask layer 14. The etching process is typically performed for a sufficient duration to insure that the surface 10S of the P-active region 10P is clear of silicon dioxide material, i.e., typically there is a brief over-etching period to insure removal of the material of the hard mask layer 14. During this etching process, the exposed portions of the isolation structures 12, which are typically also comprised of silicon dioxide, are also subjected to the etching process. As a result, there is some consumption of the isolation structures 12 during this etching process, i.e., illustrative divots 12A are formed in the exposed portions of the isolation structures 12. The depth of these divots 12A at this point in the process may vary depending upon the application, but, in one example, the depth of the divots 12A at this point in the process flow may be about 15-30 nm.
With reference to FIG. 1D, the next process operations involve removing the first patterned mask layer 16 and then performing a cleaning process to insure that the surface of the P-active region 10P is free of any undesirable residual materials prior to forming a layer of epitaxially grown semiconductor material on the P-active region 10P. The first patterned mask layer 16 may be removed using a variety of techniques, e.g., a plasma-based ashing process. The cleaning process may be a wet, dilute HF acid cleaning process that is performed for a relatively short duration. The isolation structures 12 are also exposed to this epi pre-clean process, which increases the depth of the existing divots 12A. In one illustrative example, the epi pre-clean process may increase the depth of the divots 12A by about 5-20 nm. Thus, after the isolation structures 12A are exposed to the etching process that was performed to remove the hard mask layer 16 and the epi pre-clean process, the final depth of the divots 12A due to these two process operations may be about 20-50 nm.
FIG. 1E depicts the device after a layer of channel semiconductor material 18, e.g., silicon/germanium, has been selectively formed on the P-active region 10P by preforming an epitaxial deposition process. In some applications, a relatively shallow recess (not shown) may be formed in the P-active region 10P prior to forming the channel semiconductor material 18. Typically, such a layer of channel semiconductor material 18 is not formed on the N-active region 100N where the NFET device will be formed, but that may not be the case in all applications.
Next, as shown in FIG. 1F, a second patterned mask layer 20, e.g., a patterned photoresist mask 20, is formed above the channel semiconductor material 18. The second patterned mask layer 20 covers the P-active region 10P and exposes the portion of the hard mask layer 14 that is positioned above the N-active region 10N for further processing. The second patterned mask layer 20 may be formed using traditional photolithography tools and techniques.
Then, as shown in FIG. 1G, an etching process, such as a wet etching process using a dilute HF chemistry, is performed through the second patterned mask layer 20 to remove the exposed portions of the hard mask layer 14. The etching process is typically performed for a sufficient duration to insure that the surface 10S of the N-active region 10N is clear of silicon dioxide material, i.e., typically there is a brief over-etching period to insure removal of the material of the hard mask layer 14. During this etching process, the exposed portions of the isolation structures 12, which are typically also comprised of silicon dioxide, are also subjected to the etching process. As a result, there is some consumption of the isolation structures 12 during this etching process, i.e., illustrative divots 12B are formed in the exposed portions of the isolation structures 12. The depth of these divots 12B at this point in the process may vary depending upon the application, but, in one example, the depth of the divots 12B at this point in the process flow may be about 15-30 nm.
FIG. 1H depicts the device after the second patterned mask layer 20 has been removed, e.g., by performing a plasma-based ashing process. As depicted, the process flow described above results in undesirable and uneven consumption of the material of the isolation structures 12 which adds to the overall uneven topography of the upper surface of the substrate 10. The uneven topography resulting, at least in part, from the uneven consumption of the isolation structures 12 can be problematic for several reasons. For example, the uneven topography resulting from the uneven consumption of the isolation structures 12 can make it more difficult for CMP processes to obtain planar surfaces. Additionally, if the depth of the divots (e.g., 12A or 12B) is too great, there is an increased chance that there may be a loss of gate encapsulation as processing continues. The presence of such divots may also cause an increase in the degree of undesirable “footing” of the gate materials when they are patterned to define the gate structures for the transistor devices. In some cases, the depth of the divots may be so great that there is a risk of incomplete etching for one or more of the conductive materials in the gate structures such that there is a short-circuit created between adjacent gate structures. Such a situation is sometimes referred to as the creation of undesirable “poly stringers” between adjacent gate structures. As a result, the isolation structures 12 that are subjected to excessive and/or uneven material loss during various process operations may not perform their isolation function as intended, which may result in problems such as increased leakage currents, device failure, etc.
The present disclosure is directed to various methods of forming isolation structures that may eliminate or at least reduce one or more of the problems identified above.